1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to an electrically measurable test structure that may be used to determine lithographic misalignment of vias relative to electrically active elements employed by the integrated circuit.
2. Description of the Related Art
Modern integrated circuits contain numerous structures or features, typically the size of a few micrometers. The features are placed in localized areas, and are either conductive, non-conductive or semi-conductive (i.e., rendered conductive in defined areas with dopants). A technique known as photolithography or "lithography" is used to place such features. Lithography entails radiation used to pattern a photosensitive film. An optical image is transferred to the film from a patterned mask placed in proximity to the film. The photosensitive film, i.e., "photoresist" has two main properties. First, solubility of the resist changes in response to it being exposed to appropriate radiation. Second, a hardened resist is resistant to attack by an etchant capable of removing selectively exposed conductive and/or insulative material.
According to a sequence of lithographic steps, the resist is first applied to a semiconductor topography. Next, a partially transparent mask is placed in proximity to the topography. Patterns upon the mask are projected upon the topography using various forms of radiation. Ultraviolet light is the primary form of radiation that is used, but x-rays and electron beams are growing in popularity. The radiation is transmitted through only the transparent portions of the mask plate to the photoresist film. The resist solubility of regions that are exposed to radiation is altered by a photochemical reaction. The selectively exposed resist is then washed with a solvent that preferentially removes the resist areas of higher solubility. Subsequently, the now patterned resist is exposed to an etchant that removes those portions of the topography unprotected (i.e., not covered) by the resist. Finally, the photoresist film is removed, leaving a duplicate of the mask plate pattern etched into the substrate film.
During photolithography, it is necessary that the mask plate pattern be properly aligned relative to previously formed patterns upon the topography prior to being exposed to radiation. Typically, alignment is performed using a structure known as an "alignment mark". The alignment mark includes an alignment target that is formed in a layer of the topography (henceforth referred to as "substrate"). An alignment guide formed within the mask plate can then be visually or optically aligned with the alignment mark. Alignment is achieved by moving the mask plate until the alignment guide and the alignment target are correctly positioned with respect to each other. Perfect alignment of the patterned substrate to the desired image to be printed is rarely achieved.
Several factors limit alignment accuracy. For example, the step-and-repeat method used to form a pattern upon the mask plate by its nature leads to alignment errors across the mask. This method involves repeatedly imaging a master device pattern, i.e., reticle, on the mask plate to build a rectangular array. Proper alignment of two layers requires that the corresponding mask plates of the two layers have identical arrays, which is difficult to achieve. Further, the imaged size of the mask pattern may be slightly expanded or contracted in a linear manner relative to the substrate pattern. Expansion of the image can result during the step-and-repeat method or during photolithography. Contraction of the image may be a result of thermal expansion of the substrate or the mask plate. Even if the mask and substrate dimensions are correct, the equipment used for alignment of the mask plate to the wafer topography often makes errors.
In whatever form, proper alignment is necessary to avoid failure of devices employed across an integrated circuit. For instance, if vias (i.e., conductive plugs or openings placed through interlevel dielectrics) are not properly positioned over conductive or semi-conductive elements (henceforth referred to as "electrically active areas"), integrated circuit devices that should electrically communicate with each other may, in the extreme, actually be electrically isolated from each other. Even if the extreme scenario does not occur, slight misalignment of the via to an active area may cause devices to receive voltages or current less than the designed or targeted amount.
Optimum alignment of each layer to previously patterned layers is particularly necessary as the number of layers within an integrated circuit increases. To ensure that a lithographic system is performing accurate alignment during fabrication, a test structure is often formed directly upon the wafer itself. The test structure contains features, such as active areas and contacts. Distance measurements are then made to determine how far features of the test circuit are shifted from their desired or targeted locations. Such measurements are often performed using an optical measurement system such as a scanning electron microscope ("SEM"). Unfortunately, these type of measurements are often time consuming. Further, accuracy of measurements made using an optical system may be limited by the resolution of the system or ability of the system to distinguish closely spaced objects.
It is therefore desirable to develop a test structure and method which can more rapidly determine misalignment than optical techniques. Such a method would prove beneficial in possibly locating the source of misalignment, and therefore allow for corrective measures to be taken to prevent future misalignment problems. A test structure is needed that not only discerns misalignment, but also quantifies misalignment and the direction of misalignment. Quantifying the amount and direction of misalignment provides indicia to an operator necessary for him or her to adjust for the misalignment on future wafer runs. The improved test structure might beneficially be employed prior to a wafer run, or between wafer runs to allow adjustment for subsequent lithographic alignments.